Category:Digital electronics

C

• Digital circuits (4 C, 41 P)
• Clock signal (27 P)

E

• Electronic design automation (14 C, 100 P)

F

• Finite-state machines (49 P)

I

• Integrated circuits (20 C, 171 P)

L

• Logic design (8 P)
• Logic families (39 P)
• Logic gates (1 C, 46 P)

M

• MOSFETs (7 C, 82 P)

P

• Pinball electronics (1 C, 1 P)

• Digital electronics
• Processor (computing)

0–9

• List of 4000-series integrated circuits
• 4000-series integrated circuits
• List of 7400-series integrated circuits
• 7400-series integrated circuits

A

• Additron tube
• Adiabatic circuit
• AND gate
• Antifuse
• Antistatic bag
• Antistatic device
• Asymmetric C-element
• Asynchronous serial communication

B

• Behavior tree (artificial intelligence, robotics and control)
• Beyond CMOS
• Bistability
• Bit slicing
• Bus (computing)
• Bus analyzer
• Bus encoding

C

• C-element
• C166 family
• Central processing unit
• Channel router
• Charge sharing
• CHMOS
• CMOS
• Combinational logic
• Common Electrical I/O
• Computer hardware
• Computer memory
• Computron tube
• Control unit

D

• Data processing unit
• Data storage tag
• Databending
• Datapath
• Josephson junction count
• Degradation (telecommunications)
• Delay-line memory
• Delay-insensitive minterm synthesis
• Delay-locked loop
• Design flow (EDA)
• Design for additive manufacturing
• Design for manufacturability
• Digital clock manager
• Digital lollipop
• Digital signal conditioning
• Digital signal processing
• Direct-coupled transistor logic
• Double data rate
• Dye-and-pry

E

• Early completion
• Electrostatic discharge materials
• Encoder (digital)
• Europe Card Bus

F

• Fault model
• Field-programmability
• Flip-flop (electronics)
• Frequency counter
• Front Panel Data Port
• Fuzzy electronics

G

• Glitch
• Glitch art
• Glitch removal
• Graphics processing unit

H

• Hazard (logic)
• HCMOS
• High-speed transceiver logic

I

• In-system programming
• Ingress cancellation
• Integrated circuit
• Interconnect bottleneck

J

• Jitterlyzer

L

• Leading zero
• Level shifter
• LiquidHD
• List of Wi-Fi microcontrollers
• Logic analyzer
• Logic level
• Logic optimization
• Logic probe
• Logic redundancy
• Logic synthesis
• Logical effort
• Low power flip-flop

M

• Media processor
• Memory cell (computing)
• Message Signaled Interrupts
• Metastability (electronics)
• Microprocessor
• Microprocessor chronology
• Model K (calculator)
• ModelSim
• List of MOSFET applications
• Multi-channel length
• Multi-threshold CMOS
• Multiple-emitter transistor
• MVCML

N

• NORBIT
• NT (cassette)
• Numerically controlled oscillator

O

• One-cold
• One-hot
• OR gate
• Oversampled binary image sensor

P

• Parametron
• PCMOS
• Postdigital
• Posted write
• Power gating
• Power network design (IC)
• Power optimization (EDA)
• Power–delay product
• Programmable interrupt controller
• Programmable interval timer
• Propagation time

Q

• Quad data rate
• Quantum flux parametron

R

• Random flip-flop
• Rapid single flux quantum
• Reconfigurable computing
• Register file
• Relay
• Reversible computing
• RF CMOS
• Runt pulse

S

• Schmitt trigger
• SCMOS
• Self-clocking signal
• Semiconductor memory
• Sequential logic
• SerDes
• Serial FPDP
• Shift register lookup table
• Signal edge
• Signal integrity
• Simatic
• Single-event upset
• Slave clock
• Soft error
• Static discipline
• STEbus
• Stuck-at fault
• Superconducting computing
• Switching circuit theory

T

• Three-state logic
• Time-slot interchange
• Transistor fault
• Transistor–transistor logic
• Triggering device

U

• UML state machine

V

• VISC architecture
• Vivado
• Voltage regulator module

X

• Xilinx ISE
• XOR gate

Y

• Yospace